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Overview

Infineon, NXP, BOSCH, and other leaders in the semiconductor industry have announced they will develop RISC-V based System-on-Chips (SoCs) for the automotive and Functional Safety markets. TASKING is collaborating closely with semiconductor companies and RISC-V IP suppliers to create advanced software development tools tailored for these devices.

TASKING’s RISC-V tool suite contains compilation, static analysis, debugging, tracing, performance tuning, timing, and coverage analysis tools, providing a comprehensive solution for automotive systems development.

Our compiler supports an extensive range of ISA extensions, allowing IP and SoC designers to evaluate the impact of ISA configuration changes on key optimization objectives, including code size, execution speed, power consumption, performance, and silicon area. This comprehensive capability offers a holistic view, enabling the optimization of overall system efficiency across both hardware and software domains.

Virtual ECU platform development is supported through interoperability with Synopsys VDK (Virtualizer Development Kit), Silver virtual ECU platforms, and MachineWare virtual prototypes. These integrations ensure a streamlined development process, from simulation to implementation.

Currently, TASKING’s RISC-V tools are available exclusively to RISC-V IP and SoC design teams.

BENEFITS

Performance

  • Best-in-class code-size! The compiler generates exceptionally compact code, supporting all ratified ISA extensions to reduce code size.
  • Well balanced optimization tradeoffs.
  • The compiler delivers fast-executing code while maintaining a compact memory footprint.
  • Optimal support for a device’s ISA and ISA extensions. Specify any combination of Base ISA and extensions via the command line, and the compiler adapts its code generation and optimization strategies accordingly.
  • Debug tools that suit your use case. Supporting both virtual and physical SoCs, offering solutions from low-cost, high-speed single-core run-control debugging to ultra-fast, system-level multi-core debugging. Features include instruction trace, RTOS OS/AUTOSAR advanced timing analysis, monitoring of analog and digital signals, and CAN/LIN network activity.
  • Optimizations are fine-tuned for the micro architecture of the IP and SoC providers supported by TASKING.

Reliability

  • Product development in conformance with ASPICE level 2 compliant processes.
  • The RISC-V Toolset is based on TASKING’s proprietary Viper compiler development framework, the same technology that underlies all TASKING’s compiler toolset.
  • The compiler consistently passes rigorous verification tests, including commercial, open-source, and internally developed suites. Coupled with our compliant development processes, this ensures the evidence needed to successfully achieve Functional Safety (FuSa) and cybersecurity certification when required.
  • Working closely with IP and silicon suppliers to ensure that automotive grade tools are available before silicon is introduced to the market.
  • Feature-rich SDK allows test automation, CI/CD and integration with 3rd party tools'

Safety / Cybersecurity

  • Safety and Security Manual provides easy to use and highly mature guidance for safe and secure tool use. No additional tool qualification efforts required by the user.
  • FuSa and Cybersecurity compliance certificates will become available on market demand. The tools are qualified to satisfy the requirements of FuSa standards ISO 26262, IEC 61508, ISO 25119, EN 50657, and ISO 13849, and Cybersecurity standard ISO/SAE 21434
  • Built-in static analysis to ensure your source code complies with MISRA and CERT safe and secure coding guidelines. It provides warnings when unsafe or insecure language features or constructs are used.
  • Safe and secure compiler optimization strategies. The compiler does not silently apply optimizations based on the existence of undefined behaviors in the user’s source code. Instead, it provides diagnostic messages, allowing users to address and correct any code deficiencies.