TASKING VX-toolset for TriCore v5.0r2
Release Note

Scope

This release note covers the changes between v4.4r3 and v5.0r2 of the TASKING VX-toolset for TriCore.

For release notes prior to v5.0r1, please visit the TASKING TriCore support website.

Contents

• Important Notices
• New in v5.0r2
• Fixed Issues in v5.0r2
• New in v5.0r1
• Fixed Issues in v5.0r1
• Quick start
• License information

Important Notices

HSM

Support for the special function registers (SFR) of the HSM is available through a separate installer. For security reasons related to the HSM,  Altium will verify the possible availability of the SFR installer to an end user with Infineon. Once Infineon gives Altium permission to release the SFR installer, we will make it available through a secure FTP location.

Simulator update

To support the latest AURIX derivatives hardware it is required to upgrade to the latest simulator from Infineon, TSIM v1.11.62. Therefore this version is included in this release.

DAS 4.6.0 support

The v5.0r2 has been tested with the latest DAS version 4.6.0 of Infineon. No problems have been found. It is recommended to use DAS 4.6.0  with TriCore v5.0r2. Download here.

New in v5.0r2

This section gives an overview of the most important new features and improvements in v5.0r2. See the sections with fixed issues for a complete list.

C++ Compiler update for C11 compliancy

To be able to support the C11 in the TriCore C++ Compiler, its front end has been upgraded. With this update the following new options are introduced:

Refer to TCVX-40106.

Note: in this release the option --c++0x (alias for --c++11) is still available for backwards compatibility. In the next major release this option will become obsolete (and thus removed).

Support for C++ lock-free atomic operations

Support for C++ lock-free atomic operations in machine word size has been added to this release.

The atomic operations are implemented through the use of atomic operations provided by the TriCore instruction set architecture, the implementation does not use mutexes or other locking mechanisms to stall threads.

Objects of atomic type and the data objects that are protected by atomic types shall be allocated in non-cached memory. This can either be achieved by disabling the caches or by updating the linker script language file (LSL file). In the latter case the sections in which the objects are allocated must be selected and allocated at addresses that correspond to non-cached memory.

Refer to TCVX-40247.

Multi-core hardware debug support

The TriCore debugger does now support multi-core hardware debugging. Refer to the below picture while reading the following.

• When the debugger is started with a multi-core device (AURIX) all TriCore cores of the selected derivative can be debugged. In the below picture the example tc_queens (in a multi-core variant) is debugged on TC29x.
  
• For each of the 3 TriCore core of the TC29x a separate thread is started. In the below picture the situation is: Thread core 0 is suspended, Thread core 1 is running, Thread core 2 is suspended.
  
• Each of these threads can be halted and started independent of the other threads by selecting the thread and then clicking on the pause or continue button. In the below picture the Thread core 1 has been selected (gray background color). When hitting the pause button or continue button this only effects Thread core 1.
  
• Breakpoints can be set per thread/core when the thread has been selected first. Opening the source will then only allow to set a breakpoint on the code of the selected core.
• When a Thread is selected, the Source window, the Register window, the Disassembly window are updated to the contents of the Thread (either running or halted - with the latter situation up-to-date information is shown).
  
• When the board is selected, in the below picture "Infineon TriBoard TC29X" line, all cores can be halted or started simultaneously. However when one of the threads is running and the others are suspended, then the running thread must first be suspended directly before all can be started at once via the board selection method. The same for suspending all at once.
  

Multi-core Debug

Note: multi-core hardware debug support in the script debugger (dbgtc) is planned for the next major release.

High Level Dumper new features

• New option --core-list to report the TriCore cores used in the application. Only valid for AURIX derivatives. Refer to TCVX-40079.
  
• New suboption gap-info added to --expand-symbols to report gaps in complex data types (structures and unions), between data objects and between code objects. Refer to TCVX-40074.
• New suboption callgraph added to --dump-format to report the complete callgraph of the application. Refer to TCVX-40073.

Elfpatch tool new features

The Data Reference Modification feature is extended with modification of data references inside C structures. The data references are const pointer initializers referencing global variables. The global variables can have any data type. The C structures can be defined as const. The syntax of the new structure related DRM is:

    structure: original_const_pointer_initializer = new _const_pointer_initializer;

These rules needs be included in to the function DRM file (--data-reference-modification-file=<file>). All references are symbol references. Refer to TCVX-39965.

Further the --report option is extended to be able to give a final global report on the commands executed or not executed. The -vv option is no longer really required anymore. Besides this the usage of the --report option is changed to hold the long sub-option names (like --dump-format of hldumptc). Refer to TCVX-40080.

New C compiler intrinsics functions

There are two new intrinsics function to get and set stack pointer register A10:

• void   __set_sp( void * );  // Set the A10 stack pointer
  
• void * __get_sp( void );      // Get the A10 stack pointer

When a trap service routine is called, the d15 register contains the so-called Trap Identification Number (TIN). This number identifies the cause of the trap. In the trap service routine you can test and branch on the value in d15 to reach the sub-handler for a specific TIN.

With the new intrinsic function you can use the TIN anywhere in your code:

• unsigned int __get_tin( void );  // Get the Trap Identification Number (TIN).

Multi-core example Mandelbrot for TriBoard TC27x

In the TriCore examples an example is added, named Mandelbrot, which demonstrates multi-core Mandelbrot on TriBoard tc27x. This program generates an image of the Mandelbrot set using a number of CORES. This shows the speed up of the algorithm using parallel processing on AURIX cores. The number of cores used can be set with macro CORES. The process time is printed on stdout in milliseconds. Time measurement is default enabled with macro MEASURE_TIME. The output is a binary image with 1 byte per pixel. The program prints the instructions on stdout as to how to process the output to produce a jpeg file using unix command line tool convert. The output is generated in a file at Debug/output. Output generation is default enabled with macro OUTPUT.

This example is a good starting point when starting programming a multi-core application.

New in v5.0r1

This section gives an overview of the most important new features and improvements in v5.0r1. See the sections with fixed issues for a complete list.

Support for MISRA C:2012

This release adds MISRA-C12 support to the C compiler. Rules selection and related configuration can be done from Eclipse. See the User Guide for the list of rules supported by the TriCore C compiler, PCP C compiler and ARM C Compiler (HSM).

Eclipse IDE update to version 'Kepler'

This release holds an updated version 4.3.2 of the IDE Eclipse named Kepler. For features, improvements and bug fixes please refer to the Eclipse community web-site.

New AURIX derivatives SFR support

SFR support has been added for the following AURIX derivatives: TC21x, TC22x, TC26x B-step and TC29x B-step.

TriBoard support TC27x C-step

With this release the AURIX TriBoard TC27x C-step is being supported.

Shift JIS Kanji support

In order to allow for Japanese character support on non-Japanese systems (like PCs), you can use the Shift JIS Kanji Code standard. This standard combines two successive ASCII characters to represent one Kanji character. A valid Kanji combination is only possible within the following ranges:

• First (high) byte is in the range 0x81-0x9f or 0xe0-0xef.
• Second (low) byte is in the range 0x40-0x7e or 0x80-0xfc

Compiler option -Ak and Assembler option --kanji enables support for Shift JIS encoded Kanji multi-byte characters in strings and (wide) character constants. Without this option, encodings with 0x5c as the second byte conflict with the use of the backslash ('\') as an escape character. Shift JIS in comments is supported regardless of this option.

Note that Shift JIS also includes Katakana and Hiragana.

Improved floating point configuration: --fp-model

The C compilers and control program support a new option --fp-model to control all floating point related settings. Some of those settings were formerly done with separate options. Also Eclipse got a new separate page for setting the floating point model options.

The following flags are available:

The defaults are:

• TriCore : --fp-model=2 , cFlnrSTz
• PCP : --fp-model=2 , clnrTz
  

Refer to the below table for usage of the --fp-model sub-options.

Option	Description
--fp-model=+contract	Allow the compiler to contract multiple float operations into a single operation, with different rounding  results. A possible example is fused multiply-add.
--fp-model=+float	Tell the compiler to treat variables and constants of type double as float. Because the float type takes less space, execution speed increases and code size decreases, both at the cost of less precision. Used libraries have to be built with the same setting for this option.
--fp-model=+fastlib	Allow the compiler to select faster but less accurate library functions for certain floating-point operations.
--fp-model=+nonan	Allow the compiler to ignore NaN or Inf input values. An example is to replace multiply by zero with zero.
--fp-model=+rewrite	Allow the compiler to rewrite expressions by reassociating. This might result in rounding differences and possibly different exceptions. An example is to rewrite (a*c)+(b*c) as (a+b)*c.
--fp-model=+soft	No hardware floating point instructions are generated, only calls to the software floating point library.
--fp-model=+trap	Operations trap on floating-point exceptions. Typically a trapping floating-point library is needed.
--fp-model=+negzero	Allow the compiler to ignore the sign of -0.0 values. An example is to replace (a-a) by zero.

Related pragmas

Pragma	Description
#pragma STDC FP_CONTRACT (*) (+)	Standard ISO-C99 pragma, that controls the +contract flag of --fp-model.
#pragma fp_negzero (*) (+)	Control the +negzero flag of --fp-model.
#pragma fp_nonan (*) (+)	Control the +nonan flag of --fp-model.
#pragma fp_rewrite (*) (+)	Control the +rewrite flag of --fp-model.

TriCore Compiler __atbit() and __bit are deprecated

The compiler (up to version v4.x of the toolset) was supporting __atbit() for backwards compatibility. With v5.0r1 it is deprecated. When used the following warning will be given:

You should rewrite your application as recommended.

TriCore Compiler __bit is deprecated

The compiler was supporting __bit, but actually it was exactly the same as _Bool. The __bit was used with __atbit() which has been deprecated too. Use _Bool instead.

Changes in High Level Dumper

Some updates have been made to the High Level Dumper, hldumptc. Below is a small list with the major updates. For the complete list refer to 160-39604 .

• Command-line option --data-dump-format is replaced with --hex. Both data sections as code sections will be dumped hexadecimally.
• When specifying --disassembly-intermix=-single-line one expects multilpe source lines to be displayed preceding an instruction. However, the interpretation of this command-line option is flawed such that multi-source-line mode does not get enabled. Work-around: use -iS instead.
• A new sub-option has been added to -e:   b/B +/-basic-types expand arrays with basic C types
• Restrict ELF symbol lookup to code and data for higher quality of symbols in disassembly
• Remove the -A option

Fixed issues for v5.0r2

Improvement

• TCVX-39569 - Add possiblility to create Eclipse headless build
• TCVX-39718 - Generate libc with abs() inlined
• TCVX-39723 - Optimize ld.b, extr.u instruction sequence with ld.bu
• TCVX-39805 - Additional intrinsics
• TCVX-39890 - Add loop sub-option to control the loop fusion
• TCVX-39930 - interrupt-aware stepping now always use hardware breakpoints
• TCVX-40243 - Improve license check during installation.

New Feature

• TCVX-39728 - Hardware multicore support in debugger
• TCVX-39965 - Elfpatch: new DRM feature on struct initializer
• TCVX-40073 - hldump: option for call tree generation
• TCVX-40074 - hldump: option to show gap-information on complex types
• TCVX-40079 - hldump: option to provide the number of cores
• TCVX-40080 - elfpatch: create a compact report when patching a library
• TCVX-40106 - Update the C++ compiler to support C11
• TCVX-40157 - Allow alignment attribute for typedef
• TCVX-40247 - Implement the C++11 atomic header file

Problem

• TCVX-39259 - Disassembly view puts active line on top for every instruction step
• TCVX-39750 - Inconsistent sign extension in ctc
• TCVX-39931 - breakpoint set in Disassembly view is disabled after relaunching session
• TCVX-39938 - Registers view behaves erratically when switching groups
• TCVX-39949 - Symbolic Register view does not open for certain registers
• TCVX-39963 - Symbolic Register view does not update directly after launch
• TCVX-39968 - When using GROUPing, the order of the ROM copies of initialized data is different to their RAM order
• TCVX-39979 - breakpoint disappear after reload application
• TCVX-39997 - .FLOAT instruction leads to storage with reverse endiannes incompatible with compiler's float
• TCVX-40015 - Tail merger fail for store with different Dx sign extended
• TCVX-40033 - Incorrect bitfield merging
• TCVX-40081 - Incorrect instruction selection loop optimization for signed char or short count loop counter wrap
• TCVX-40088 - Illegal reordering of volatile accesses
• TCVX-40093 - no error reported when breakpoint cannot be placed
• TCVX-40094 - stack breakpoint only works once
• TCVX-40107 - ctc -Of leads to destruction of A15/D15 registers without restore
• TCVX-40125 - -Oy (Peephole Optimizer) causes loss of sign by zero extension of upper halfword
• TCVX-40141 - ctc S911: internal consistency check failed / preprocessing
• TCVX-40156 - Generate warning instead of error when alignment attribute is used for an automatic object.
• TCVX-40175 - ctc S911: internal consistency check failed / preprocessing fails
• TCVX-40193 - Script debugger file I/O dysfunctional
• TCVX-40244 - Computer ID calculation for node locked client may fail

The list of open issues for v5.0r2 can be found on the internet.

The list of open MCS issues for v2.0r1 can be found on the internet.

Fixed issues for v5.0r1

Improvement

• 160-39523 - __bit is equal to _Bool, __bit is superfluous.
• 160-39604 - Multiple fixes in high level dump tool
• 160-39652 - --fp-model=C/c replaces --no-macs
• 160-39714 - Remove superfluous program status word read from floating point FPU run-time functions.
• 160-39717 - Generate FPU compare instruction sequence always inline
• 160-39817 - Deprecate __atbit(), it is superfluous
• 160-39895 - Simplify startup configuration of TC1 and TC2
• 160-39959 - Disable code compaction for run time floating point funtions.

New Feature

• 160-35995 - Do not stop inside an interrupt routine when using OCDS hardware breakpoint
• 160-38487 - Debugger lacks option to load Intel hex file
• 160-39603 - New TSIM v1.11.61 needs to be included in product
• 160-39683 - Added --fp-model option
• 160-39734 - Support MISRA C:2012
• 160-39801 - ISO C99 IEEE 754 floating point functions need to be implemented (e.g. fesetround and fegetround)
• 160-39811 - SFR support for TC22x
• 160-39829 - SFR support for TC26x B-step
• 160-39867 - TriBoard TC27xC support
• 160-39881 - SFR support for TC29x B-step
• 160-39955 - Shift JIS Kanji support required
• 160-39956 - SFR support for TC21x

Problem

• 160-37612 - From Eclipse import: example project tcpip can not be extracted on Windows Vista, Windows 7 and Windows 8
• 160-38365 - dependency scan for C++ files: --dep-file option not passed to C++ compiler
• 160-38550 - disassembly may be incorrect due to misalignment
• 160-38583 - erroneous MISRA 10.5 / 12.8 violation
• 160-38604 - assembler should treat third operand of rsubs.u as signed
• 160-39573 - constant propagation optimization causes incorrect result
• 160-39593 - ctc -Om (SIMD) uses MIN instead of MAX, resulting in incorrect number of loop iterations
• 160-39599 - Compiler should treat third operand of rsubs.u as signed
• 160-39612 - ctc S917: internal consistency check failed
• 160-39615 - ARM debugger does not work
• 160-39619 - S911: internal consistency check failed - please report
• 160-39620 - astc error: Segmentation fault due to duplicate labels
• 160-39632 - ltc E821: syntax error: base derivative tc27xb not found for derivative my_tc27xb
• 160-39639 - ctc S917: internal consistency check failed - please report on unary with -OP
• 160-39644 - tc1793.lsl incorrect address entry for pflash1
• 160-39670 - ctc erroneously optimizes function call between disable enable intrinsics
• 160-39680 - debugger fails to display bitstruct member contents correctly
• 160-39688 - Link error: "syntax error: base derivative tc27xb not found for derivative my_tc27xb"
• 160-39691 - Wrong entries in Copy Table when putting bss (clear) sections in output sections
• 160-39697 - ctc error S917 caused by nested struct union
• 160-39703 - ctc preprocessor ignores definitions in nested includes
• 160-39716 - FPU compare result should not include denorm bit.
• 160-39721 - Do not loop optimize for a volatile loop iterator
• 160-39765 - Selecting include path for missing directory generates invalid make file
• 160-39770 - ctc S900: internal consistency check failed - please report
• 160-39783 - atof does not always correctly convert constants with a "binary-exponent-part" ('p')
• 160-39785 - Incorrect processing of printf "%a" format specifier
• 160-39787 - ISO C99 strtof("INFINITY") not supported
• 160-39788 - ISO C99 macro INFINITY is missing
• 160-39789 - ISO C99 macros FP_NAN, FP_INFINITE, etc missing
• 160-39790 - Missing ISO C99 floating point library functions
• 160-39792 - ISO C99 macros FE_TONEAREST, FE_UPWARD, etc missing
• 160-39793 - ISO C99 macros/functions MATH_* macros and math_errhandling missing
• 160-39796 - Missing compiler diagnostic for too large floating constant
• 160-39797 - Expecting a compiler warning when using an incomplete type in a union
• 160-39802 - ISO C99 IEEE 754 floating point functions prototype has changed
• 160-39807 - Incorrect description of implementation defined behavior of bitwise shif operations.
• 160-39883 - store bit optimization on volatile bit
• 160-39914 - Aurix tc_blink download fails after cold boot.
• 160-39940 - Single entry vector table address is 0xa00f07f8
• 160-39960 - Generate 64-bit immediate values inline floating point run-time.
• 167-120 - Remove MCS from TC23x and TC23x_adas lsl

The list of open TriCore issues for v5.0r1 can be found on the internet.

The list of open MCS issues for v2.0r1 can be found on the internet.

Quick start

For a quick start, just start the TriCore Eclipse IDE from the Start menu. This will start the Eclipse based development environment. You will be asked to select a workspace. In case you used Eclipse before it is recommended to select a new workspace. After clicking OK, you will see the 'Welcome' view. On this view you will see icons that link to specific information. You can, for example, select the 'Samples' icon and import the TriCore project examples, PCP project examples, MCS project examples, 8051 project examples and/or ARM example projects.

Another icon on the Welcome page, the 'First Steps' icon, links to the 'TriCore Getting Started' document. This is a good starting point for exploring the capabilities of the environment and the tools.

License Information

TASKING products are protected with TASKING license management software.

License key

You need a license key when you install a TASKING product on a computer. When you order a TASKING product from Altium or one of its distributors, a license key will be sent to you by email or on paper.

See the Getting Started with the TASKING VX-toolset for TriCore guide for information on obtaining a license.

Local TASKING License Server (not applicable to evaluation licenses)

If you have ordered a TASKING product with a floating license, you can have it serviced by the Remote TASKING License Server (the most convenient solution) or through a Local TASKING License Server (in case you have no external network access for example). Consult your Altium representative for assistance on deciding what the best setup would be for your situation.

If you like to setup up a local license server, we kindly refer you for more information to Support for TASKING License Management System (TLM) on our website. Here you can also download the Local TASKING License Server package.

It is advised that you install the Local TASKING License Server before you install products that require this server.