TASKING TriCore VX-Toolset v2.2r1

RELEASE NOTE


SUMMARY

This release note describes the changes and new features of all TASKING TriCore products since v2.1r1.

The following parts are described:

The main reasons for this release are:

IMPORTANT NOTE

The derivatives TC10GP, TC1775A, TC1920A, Raptor and Rider-D have become obsolete. These processors are no longer supported as of this version v2.2r1 of the TriCore VX-toolset.


INTRODUCTION TO THE VX-TOOLSET

As you may have noticed the letters VX are added to the name of this new TASKING TriCore toolset. VX is short for Viper eXperience, and it indicates that this toolset incorporates the new generation VIPER DSP-C compiler technology. This compiler has been developed in-house by Altium and offers true state-of-the-art code generation. Furthermore specific DSP optimizations have been added, so you will find an improved performance of the compiler in both generated code size and run-time speed.

The compiler offers full compliance with the latest ISO C 1999 standard, for instance the _Bool and long long data types are available and ready for use.

In our strive for being in accordance with the TriCore EABI (Embedded Application Binary Interface), we have introduced the ELF/DWARF 2 object format. This smoothes the integration with many third party products such as RTOS's, software libraries and debuggers. For this purpose the assembler and linker have been redesigned as well. The new linker comes with an enhanced Linker Script Language (LSL) that replaces its predecessor DEscriptive Language For Embedded Environments (DELFEE).

With the upgrade to the Viper technology it turned out to be not possible to maintain full backwards compatibility. However, we have included a migration tool to help you convert a project, originally set up for a previous TriCore toolset, to one that will build with this new toolset.


EDE

New derivative support

New TriCore derivatives are support within EDE, within menu 'Project | Project Options...' page 'Processor | Processor Definition':

MISRA-C:2004

Enhanced MISRA C support introduced in EDE, for the new MISRA-C:2004 standard. As well as support for required and advisory rules and the ability to treat errors as warnings.

Debug Access Server (DAS)

Our debugger CrossViewPro now also supports Infineon's new Debug Access Server (DAS). As a service we offer both the OCDS/GDI as well as the DAS implementation as a transitional stage within the TriCore VX-toolset v2.2r1.

Silicon bug workarounds

The silicon bug workarounds now use the latest naming convention and only silicon bug workarounds that are relevant for a specific derivative are displayed. Options have been added to easily turn on/off all silicon bug workarounds for a particular derivative. Within menu 'Project | Project Options...' page 'Processor | Bypasses' the new silicon bug workarounds can be found.

TCP/IP stack

TCP/IP stack reference design added as a project example within EDE.


C++ COMPILER

No new/changed features.


C COMPILER

Compiler toolspeed improvements

The toolspeed of the compiler has been improved in several areas. For example the preprocessor has been improved to handle large include structures faster and more effectively.

Code performance improvements

Significant code performance increase through additional conditional instructions and FPU optimization improvements.

MISRA-C:2004

Enhanced MISRA C support introduced in the compiler, for the new MISRA-C:2004 standard.

Silicon bug workarounds

The silicon bug workarounds now use the latest naming convention, as used/defined by Infineon. Options have been added to easily turn on all silicon bug workarounds for a particular derivative:

cpu_tc.065

The compiler will insert a NOP instruction before a jump, when a label is directly followed an unconditional jump.

cpu_tc.068

The compiler inserts a disable and two NOP instructions before each dvinit instruction (and if necessary an enable after tge dvinit).

cpu_tc.069

The compiler inserts a NOP instruction after each rslcx instruction.

cpu_tc.070

The compiler inserts a NOP instruction before a loop instruction, when a conditional jump, based on the value in an address register, is directly followed by a loop instruction.
The compiler inserts two NOP instructions before a loop instruction, when a conditional jump, based on the value in an data register, is directly followed by a loop instruction.

cpu_tc.071

The compiler inserts a NOP instruction before a loop instruction, when a label is directly followed by an unconditional loop instruction.

cpu_tc.072

The compiler inserts a NOP instruction before a loop instruction, when an instruction that updates an address register is followed by a conditional loop instruction which uses this address register.


ASSEMBLER

PCP

Several problems with the PCP assembler have been fixed in major maintenance.

Instructions '.byte' and '.half' are no longer allowed by the PCP assembler. These instructions are smaller than the MAU (Minimum Addressable Unit) size and are therefore no longer supported.

New builtin functions have been introduced for the PCP assembler:

cpu_tc.065

The assembler gives a warning when a label is directly followed by an unconditional jump, only when debug information is turned off.

cpu_tc.068

The assembler gives a warning when a dvinit instruction is not preceded by a disable and two NOP instructions.

cpu_tc.069

The assembler gives a warning when a rslcx instruction is not followed by a NOP instruction.

cpu_tc.070

The assembler gives a warning when a conditional jump, based on the value in an address register, is directly followed by a loop instruction.
The assembler gives a warning when a conditional jump, based on the value in a data register, is directly followed by a loop instruction or when only one single NOP instruction is in between.

cpu_tc.071

The assembler gives a warning when a label is directly followed by an unconditional loop instruction, only when debug information is turned off.

cpu_tc.072

The assembler gives a warning when an instruction that updates an address register is followed by a conditional loop instruction which uses this address register.

cpu_tc.074

The assembler encodes the LOOPU instruction in such a way that bits 12-15 get the value 1.


LIBRARIES

The libraries have been updated to prevent new silicon bugs to trigger. The libraries are rebuild, using the new compiler and assembler.

Protected libraries are now available for each TriCore derivative (with all their specific silicon bug workarounds). The libraries can be found in for example the subdirectory "lib/p/tc1100" within the TriCore product directory.


LINKER

Various general improvements and solving of reported problems.


UTILITIES

Control Program

You can pass all new silicon bugs to the control program by using the --silicon-bug option. The control program recognizes the silicon bugs and passes the options to the correct tool(s).


CROSSVIEW PRO

Debug Access Server (DAS)

CrossViewPro supports Infineon's new Debug Access Server (DAS), which is the successor of the OCDS/GDI interface. DAS enables on-chip debugging using Infineon TriBoards, connected locally or remotely.

As a service we offer both the OCDS/GDI as well as the DAS implementation as a transitional stage within the TriCore VX-toolset v2.2r1.


Copyright 2005 Altium BV