This release note covers the most relevant changes between v5.2r1 and v6.0r1 of the TASKING VX-toolset for ARM Cortex-M.
For release notes prior to v6.0r1, please visit the TASKING ARM support website.
This release note focusses on the introduction of support for Traveo II devices.
Release v6.0r1 is a 64-bit product. It shall be installed on 64-bit versions of the Windows operating system. The release was tested on Windows 10 64-bit.
Release v6.0r1 does not perform a license check when the Eclipse IDE is started. This means that the IDE can be used for non-tool related activities without claiming a license seat. For example, to do a code review or to look at a linker map file. It also means that if there is no valid license this will no longer be reported at IDE start-up but only when a tool is started which requires a valid license.
The Cypress Traveo II Sample Driver Library (SDL) v6.6.0 is partially distributed with TASKING release v6.0r1. It is included in the Eclipse plug-in for Cypress device support (com.tasking.arm.vendors.cypress_1.1.0.0). There are modifications in the SDL start-up code, needed to make it work with the TASKING tools. These modifications are designated with the use of the __TASKING__ pre-processor macro.
The TASKING debugger can be used with the Traveo II evaluation boards. A SEGGER J-Link probe is required to connect the board to the host PC. A recent version of the J-Link BASE is sufficient.
All executable files in this release have the following build number: Build 22022851.
This release adds support for the Cypress Traveo II device family from Infineon. This includes:
In principal all full-device application projects for Traveo II shall be setup as a multi-core project in the IDE. There is always one project for the CM0 core which serves as the base project. Depending on the actual device there will be an additional project for the CM4 core or the single CM7 core, two additional projects for the dual CM7 cores, or one additional project for the dual CM7 cores combined (so-called virtual VM7 core project). The additional core projects shall be referenced projects in the base CM0 project. When the non-base projects are built, an intermediate output file is produced by the linker. These intermediate files are input to the base project, which executes the final locating process and produces the absolute object files. These absolute files can be downloaded to the target device by means of the debugger.
When creating a new project for a Traveo II device, you select a specific device by means of the processor selection dialog. This dialog offers an expandable tree structure. Select 'Cypress', select a Traveo II series (e.g. Traveo II CYT4BF series) and select a specific chip/core combination (e.g. CYT4BFCCHD_M7). The M0/M4/M7 selection must be made explicitly because the CM0 core has a different ARM architecture profile than the other cores and the compiler needs to be made aware of this. To use the start-up code provided through the SDL library, enable "Add startup file(s) to the project". (See the example projects for additional hints.)
The ITCM and DTCM memories of the CM7 cores are 'reserved' memories in the linker LSL files. This implies that by default nothing will be located in these memories by the linker. Sections can be located in these memories explicitly by the user in two ways. One way is by manually adding 'select' statements to the LSL files. Specific sections can be selected using section name patterns. Section names can be defined by means of the section naming options and pragmas supported by the compiler. The other way is by adding the compiler '__tcm' memory qualifier (or pragma) to selected functions and data objects in the source code. The TASKING startup code will automatically copy TCM-designated sections from ROM to RAM.
The TASKING tools support application development for a dual-core CM7 cluster in a single project. The linker and the LSL files define a so-called virtual core for this purpose, called VM7. The advantage of a virtual-core project is that code and data in memory can be shared between the two CM7 cores. Also, code and data can automatically be replicated in the local TCM memories of each CM7 core. This is done by specifying the '__clone' qualifier with function or data object definitions which are to be replicated. The TASKING startup code will automatically copy cloned sections from ROM to both TCM memories.
Because the object files for both CM7 cores of the dual-core cluster are built by the same project, items which are to be associated with a specific core must be designated as such in the application source code. Code or data for a specific core's TCM memory shall be defined using the '__tcm0' or '__tcm1' memory qualifier. Exception handling functions shall be defined using the __interrupt0 or __interrupt1 qualifier. This is different from projects which are built for a single CM7 core (of a dual-core cluster) because in those projects the generic '__tcm' and '__interrupt' qualifiers are to be used and the '__clone' qualifier is useless.
With functions which are shared or cloned it may sometimes be necessary to know at run-time on which CM7 core they are running. This can be accomplished by implementing a run-time check on the CPUSS_IDENTITY register and looking for the value of the bus master ID. The value is either 13 (CPUSS_MS_ID_CM7_1 Master ID for CM7_1) or 14 (CPUSS_MS_ID_CM7_0 Master ID for CM7_0).
Vector tables are generated by the TASKING linker by means of specific constructs in the project LSL file and the use of the __interrupt function qualifier in the source code. Vector tables can be copied from ROM to RAM automatically by the TASKING start-up code. To select this feature, the __core_VECTOR_TABLE_RAM_COPY macro shall be specified to the linker, where core is from the set CM0/CM4/CM7_0/CM7_1.
For calls from Flash (e.g. main function) into ITCM and for calls from ITCM into Flash (e.g. SDL library function) absolute calls are needed because PC-relative calls cannot bridge the gap in the Traveo II memory map. The compiler generates PC-relative calls by default, which will result in an R_ARM_THM_CALL relocation error from the linker. Either compile with the "--call=far" option set or use "#pragma call far" in the source code. The most fine-grained control over such calls can be obtained by using the '__far' qualifier on extern function declarations. Only functions declared with this qualifier will be called indirectly. Using the --long-branch-veneer option of the linker to automatically resolve out-of-range PC-relative calls is discouraged. It is cumbersome to use in multi-core projects (see also next paragraph) and it does not work for calls from ITCM RAM back to Flash/ROM.
When compiling and linking from the command line it is most convenient to use the control program ('ccarm') and specify the --cpu, --processors, --lsl-core and --new-task options. As the device support is provided by means of vendor-dependent Eclipse plug-in files, the path names to be used on the command line are rather cumbersome. Refer to the "TASKING VX-toolset for ARM User Guide" for details on how to build projects from the command line. Here's an example of how to use the option --long-branch-veneer in a multi-core project:
ccarm --processors=$ARM_ROOT/carm/eclipse/plugins/com.tasking.arm.vendors.cypress_1.1.0.0/etc/processors.xml -CCYT4BFCCHD_M0 -co -v -t cm0_a.c ccarm --processors=$ARM_ROOT/carm/eclipse/plugins/com.tasking.arm.vendors.cypress_1.1.0.0/etc/processors.xml -CCYT4BFCCHD_M0 -co -v -t cm0_b.c ccarm --processors=$ARM_ROOT/carm/eclipse/plugins/com.tasking.arm.vendors.cypress_1.1.0.0/etc/processors.xml -CCYT4BFCCHD_M7 -co -v -t cm7_0_x.c ccarm --processors=$ARM_ROOT/carm/eclipse/plugins/com.tasking.arm.vendors.cypress_1.1.0.0/etc/processors.xml -CCYT4BFCCHD_M7 -co -v -t cm7_0_y.c ccarm --processors=$ARM_ROOT/carm/eclipse/plugins/com.tasking.arm.vendors.cypress_1.1.0.0/etc/processors.xml -CCYT4BFCCHD_M7 -co -v -t cm7_1_p.c ccarm --processors=$ARM_ROOT/carm/eclipse/plugins/com.tasking.arm.vendors.cypress_1.1.0.0/etc/processors.xml -CCYT4BFCCHD_M7 -co -v -t cm7_1_q.c
ccarm --processors=$ARM_ROOT/carm/eclipse/plugins/com.tasking.arm.vendors.cypress_1.1.0.0/etc/processors.xml \ -Wl-I$ARM_ROOT/carm/eclipse/plugins/com.tasking.arm.vendors.cypress_1.1.0.0/include.lsl -CCYT4BFCCHD_M0 cm0_a.obj cm0_b.obj \ --new-task=cm7_0,cm7_0_x.obj,cm7_0_y.obj,-CARMv7EM,--long-branch-veneers,-L$ARM_ROOT/carm/lib/v7EM/le/VFPv5,-lcthumb,-lrtthumb \ --new-task=cm7_1,cm7_1_p.obj,cm7_1_q.obj,-CARMv7EM,--long-branch-veneers,-L$ARM_ROOT/carm/lib/v7EM/le/VFPv5,-lcthumb,-lrtthumb
Some limitations exist when debugging multi-core projects on the hardware. These limitations pertain to differences between hard-reset and soft-reset of the device, setting of breakpoints in TCM memories and halting specific cores of the device while a multi-core application is running. Note that in SDL based applications the additional cores are started by the application running on the CM0 base core.
This release supports the C11 language and library features as defined by the ISO C standard. With the C compiler option --iso you select the ISO C standard. C90 (option value '90') is also referred to as the "ANSI C standard". C99 (option value '99') refers to the ISO/IEC 9899:1999 (E) standard. C11 (option value '11') refers to the ISO/IEC 9899:2011 (E) standard. C11 is the default. All unconditional (mandatory) C11 features are supported. Of the conditional features which are introduced by C11 the Atomic feature is supported. Support can be checked by means of the conditional feature macros as defined by the C standard (section 6.10.8.3).
This release fully supports the C++14 language and library features as defined by the ISO C++ standard. With the C++ compiler option --c++ you select the ISO C++ standard. Option value '03' refers to ISO/IEC 14882:2003, '11' refers to ISO/IEC 14882:2011, '14' refers to ISO/IEC 14882:2014. Selecting C++11 or later also enables exceptions. The old --c++<**> options are deprecated. The new options will also automatically select the appropriate C++ libraries. C++14 is the default. Refer to the user manual for details.
The option --io-streams only affects compilation in C++03 mode and it is no longer necessary to provide a language version with it.
By default the C++ compiler now uses the built-in type wchar_t. It is no longer needed to specify option --wchar_t-keyword for this. The former default, using a type definition for wchar_t, can now be obtained by specifying the new option --no-wchar_t-keyword.
The TASKING RTOS, TASKING Software Platform for STM32 and TASKING Pin Mapper for STM32, designated as Bonus Technology in previous releases, are discontinued.
For a quick start, just start the IDE from the Start menu. This will start the Eclipse based development environment. You will be asked to select a workspace. In case you used Eclipse before it is recommended to select a new workspace. After clicking OK, you will see the 'Welcome' view. On this view you will see icons that link to specific information.
TASKING products are protected with TASKING license management software.
You need a license key when you install a TASKING product on a computer. When you order a TASKING product from TASKING or one of its distributors, a license key will be sent to you by email or on paper.
See the TASKING License Management (TLM) Support page for information on obtaining a license.